0- in is an assertion based verification tool .The 0-In V2.0 ABV Suite offers powerful tools for designers and verification engineers throughout the entire development cycle. The ABV Suite features comprehensive assertion-based verification methodology that works from block-level through system-level verification, including regression testing, simulation acceleration, and hardware emulation. 0-In products are all simulator- and test bench-independent, making them applicable

throughout the verification process. V2.0 adds support for Accellera assertion standards, improves simulation and formal verification performance and incorporates new coverage metrics for assertions.

The 0-in ABV SUITE has the following products:

0-In Checklist rapidly and automatically finds common RTL coding errors, including simulation-to-synthesis mismatch errors, cross-domain clocking errors, and many other syntactic and semantic problems.

0-In Check is a complete assertion specification and management system, including comment-based directive specification, RTL-inferencing, assertion synthesis and a rich library of over 70 Verilog assertion checkers.

0-In Search uses dynamic formal verification (DFV) technology to find bugs missed by simulation in large RTL designs.

0-In Confirm uses "deep counterexample technology" to find deep bugs missed by all other verification methods in large RTL designs.

0-In CheckerWare Monitors are protocol monitors used in simulation and formal verification that capture, check and generate structural coverage metrics for protocol rules on complex standard industry-standard busses and interfaces such as PCI Express, HyperTransport, SPI-4.2, DDR SDRAM, AGP 8X and AMBA.